When audio samples are de-embedded from a video stream, the timing of the audio samples must be reconstructed. Usually the audio samples are synchronous with the video timing. There is generally a precise ratio of the audio sampling frequency with respect to the video sampling frequency. To transmit the audio signal via a serial interface (e.g., an AES/EBU (Audio Engineering Society/European Broadcasting Union), SPDIF (Sony/Philips Digital Interconnect Format), or an I2S (Inter-IC Sound, or Integrated Interchip Sound) interface), an audio clock signal at a submultiple of the higher signal sampling rate, such as a video sampling rate, is required (e.g., a video sample rate that is 128 times an audio sampling rate). Several techniques are conventionally used to generate the required synchronous audio clock signal from a higher frequency video clock signal. Most involve using well-known phase-locked loop techniques incorporating a VCO (“voltage-controlled oscillator”) to generate the audio clock signal.
A conventional way to generate a synchronized audio clock signal from a higher frequency video clock signal employs a VCO in a PLL (“phase-locked loop”), which cannot be easily implemented in commonly used digital circuits such as FPGAs (“field programmable gate arrays”) or other programmable integrated circuits (ICs). An alternative is direct digital synthesis using an NCO (“numerically controlled oscillator”), which involves a DAC (“digital-to-analog converter”) and an analog filter, rather than a VCO in a PLL. There are commonly available ASSP (“application-specific signal processor”) chips that use these techniques. However, the cost is a significant disadvantage in terms of board space and end product price, especially if there are multiple video and audio streams to be de-embedded.
FPGAs are commonly used for processing video signals. Handling embedded audio is also a task that can conveniently be done in an FPGA. Currently, however, clock signal generation (and sometimes the signal de-embedding itself) is done by application specific standard product (“ASSP”) chips external to the FPGA, at significant added cost. It would be advantageous to have the audio clock signal generation done inside the FPGA. This is possible using PLL resources of the FPGA. However, there are typically few PLLs in an FPGA, and they are often needed for other clocking tasks. Furthermore, when many channels are present, many PLLs are required, possibly more than the number available in the FPGA.
An FPGA or other programmable IC that can generate an audio clock signal from a video stream using commonly available resources would enable the design of a compact integrated circuit without the need for resource-expensive circuit elements such as PLLs, NCOs, DACs, or ASSPs. Thus, there is a need for a circuit and related method to generate an audio clock signal inside a programmable IC in a way that uses commonly available resources that avoid the disadvantages of conventional approaches.